Technical Papers

A Low Voltage, Low Power P-Channel Memory For Embedded and System-on-a-Chip Applications
A presentation technical paper presented at the IEEE's Non-Volatile Semiconductor Memory Workshop, 1998.

View Document: PMC_IEEE-98.pdf

pFLASH® Architecture Advantages
Two transistors (2T) PMOS cell is the quickest way to realize a reliable, fast programming, low power and low cost reprogrammable nonvolatile memory product. Only with the combination of 2T and P-Channel MOS device will result in disturbance free re-programmable nonvolatile memory. The absence of disturbance at both program and read cycles eliminate majority of the subtle reliability challenge for all of the other Flash technology in the industry today. This unique combination also enable the Band-To-Band Tunneling program which is the most efficient methodology for the least amount of reliability hazard related to endurance and data retention performance. The combination of BTBT program and Channel Fowler-Nordheim (CFN) erase not only result in the minimum power consumption but also the most scalable NOR Flash technology.

View Document: pFLASH Memory Architecture Advantages 2003.pdf

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